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LTC3409 600mA Low VIN Buck Regulator in 3mm x 3mm DFN DESCRIPTIO
The LTC(R)3409 is a high efficiency, monolithic synchronous buck regulator using a constant frequency, current mode architecture. The output voltage is adjusted via an external resistor divider. Fixed switching frequencies of 1.7MHz and 2.6MHz are supported. Alternatively, an internal PLL will synchronize to an external clock in the frequency range of 1MHz to 3MHz. This range of switching frequencies allows the use of small surface mount inductors and capacitors, including ceramics. Supply current during Burst Mode operation is only 65A dropping to <1A in shutdown. The 1.6V to 5.5V input voltage range makes the LTC3409 ideally suited for single cell Li-Ion, Li-Metal and 2-cell alkaline, NiCd or NiMH battery-powered applications. 100% duty cycle capability provides low dropout operation, extending battery life in portable systems. Burst Mode operation can be userenabled, increasing efficiency at light loads, further extending battery life. The internal synchronous switch increases efficiency and eliminates the need for an external Schottky diode. Internal soft-start offers controlled output voltage rise time at start-up without the need for external components.
, LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode is a registered trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131.
FEATURES

1.6V to 5.5V Input Voltage Range Internal Soft-Start Selectable 1.7MHz or 2.6MHz Constant Frequency Operation Internal Oscillator can be Synchronizable to an External Clock, 1MHz to 3MHz Range High Efficiency: Up to 95% Very Low Quiescent Current: Only 65A During Burst Mode(R) Operation 600mA Output Current (VIN = 1.8V, VOUT = 1.2V) 750mA Peak Inductor Current No Schottky Diode Required Low Dropout Operation: 100% Duty Cycle 0.613V Reference Voltage Stable with Ceramic Capacitors Shutdown Mode Draws <1A Supply Current Current Mode Operation for Excellent Line and Load Transient Response Overtemperature Protection Available in a Low Profile (0.75mm) 8-Lead (3mm x 3mm) DFN Package
APPLICATIO S

Cellular Phones Digital Cameras MP3 Players
TYPICAL APPLICATIO
Burst Mode Efficiency, 1.8VOUT
100 90 2.5VIN, BURST 4.2VIN, BURST 3.6VIN, BURST 0 POWER LOST 3.6VIN, BURST 0.1
POWER LOSS (W)
High Efficiency Step-Down Converter
VIN 1.8V TO 5.5V LTC3409 SW VIN RUN MODE SYNC *SUMIDA CDRH2D18/LD VFB GND 133k 255k 2.2H* 10pF 10F CER
EFFICIENCY (%)
80 70
4.7F CER
VOUT 1.8V
60 50 40 30 20
3409 TA01
10 0 0.1 1 10 100 LOAD CURRENT (mA) 1000
3409 TA01b
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1.0
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LTC3409
ABSOLUTE
(Note 1)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW VFB GND VIN VIN 1 2 3 4 9 8 7 6 5 SYNC RUN SW MODE
Input Supply Voltage .................................. - 0.3V to 6V RUN, VFB, MODE, SYNC Voltages . - 0.3V to (VIN + 0.3V) SW Voltage ................................... - 0.3V to (VIN + 0.3V) Operating Temperature Range (Note 2) .. - 40C to 85C Junction Temperature (Note 3) ............................ 125C Storage Temperature Range ................ - 65C to 125C
ORDER PART NUMBER LTC3409EDD
DD PACKAGE 8-LEAD (3mm x 3mm) PLASTIC DFN
TJMAX = 125C, JA = 43C/ W EXPOSED PAD (PIN 9) IS GND MUST BE SOLDERED TO PCB
DD PART MARKING LBNM
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VIN = 2.2V unless otherwise specified.
SYMBOL VRUN IRUN VMODE IMODE VSYNCTH ISYNC VFB PARAMETER RUN Threshold RUN Leakage Current MODE Threshold MODE Leakage Current SYNC Threshold SYNC Leakage Current Regulated Feedback Voltage (Note 4) TA = 25C (Note 4) 0C TA 85C (Note 4) -40C TA 85C VOVL = VFBOVL - VFB (Note 6) (Note 4) IOUT = 100mA, 1.6V < VIN < 5.5V VIN = 2.2V, VFB = 0.5V or VOUT = 90%, Duty Cycle < 35%

CONDITIONS
MIN 0.3 0.3 0.3 0.6007 0.5992 0.5977 35
TYP 0.65 0.01 0.65 0.01 0.65 0.01 0.6130 0.6130 0.6130 61 0.04 0.04
MAX 1.1 1 1.1 1 1.1 1 0.6252 0.6268 0.6283 30 85 0.4 0.4 1.3
UNITS V A V A V A V V V nA mV %/V %/V A %
IVFB VOVL VFB VOUT IPK VLOADREG VIN IS
Feedback Current VFBOVL Overvoltage Lockout Reference Voltage Line Regulation Output Voltage Line Regulation Peak Inductor Current Output Voltage Load Regulation Input Voltage Range Input DC Bias Current Active Mode Sleep Mode Shutdown Nominal Oscillator Frequency SYNC Threshold Minimum SYNC Pin Frequency Maximum SYNC Pin Frequency Minimum SYNC Pulse Width Soft-Start Period RUN (Note 5) VOUT = 90%, ILOAD = 0A VOUT = 103%, ILOAD = 0A VRUN = 0V, VIN = 5.5V SYNC = GND SYNC = VIN When SYNC Input is Toggling (Note 7)

0.75
1 0.5
1.6 350 65 0.1 0.9 1.8 1.7 2.6 0.63 1 3 100 1
5.5 475 120 5 2.1 3.0
fOSC SYNC TH SYNC fMIN SYNC fMAX SYNC PW tSS
2
U
V A A A MHz MHz V MHz MHz ns ms
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LTC3409
ELECTRICAL CHARACTERISTICS
The denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25C. VIN = 2.2V unless otherwise specified.
SYMBOL SYNC tO RPFET RNFET ILSW PARAMETER SYNC Timeout RDS(ON) of P-Channel FET RDS(ON) of N-Channel FET SW Leakage CONDITIONS Delay from Removal of EXT CLK Until Fixed Frequency Operation Begins (Note 7) ISW = 100mA, Wafer Level ISW = 100mA, DD Package ISW = 100mA, Wafer Level ISW = 100mA, DD Package VRUN = 0V, VSW = 0V or 5V, VIN = 5V MIN TYP 30 0.33 0.35 0.22 0.25 0.1 3 MAX UNITS s A
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LTC3409E is guaranteed to meet performance specifications from 0C to 70C. Specifications over the -40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: LTC3409: TJ = TA + (PD)(43C/W) This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Overtemperature protection becomes active at a junction temperature greater than the maximum operating junction temperature. Continuous operation above the specified maximum operating junction temperature may impair device reliability.
Note 4: The LTC3409 is tested in a proprietary test mode that connects VFB to the output of the error amplifier. Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. Note 6: VOVL is the amount VFB must exceed the regulated feedback voltage. Note 7: Determined by design, not production tested.
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LTC3409 TYPICAL PERFOR A CE CHARACTERISTICS
(From Typical Application on the front page except for the resistive divider resistor values) Efficiency/Power Lost vs Load Current, VOUT = 1.8V
100 90 80 70
EFFICIENCY (%)
1 2
EFFICIENCY (%)
60 50 40 30 20 10 0 0.1 1 10 100 LOAD CURRENT (mA) 1000
3409 G01
60 50 40 30 20 10 0 1.5 IOUT = 0.1mA IOUT = 1mA IOUT = 10mA 2.5 IOUT = 100mA IOUT = 600mA IOUT = 800mA 5.5
3409 G02
EFFICIENCY (%)
3 8 10 12
45
6
7 11 9
1: 2.5VIN, BURST 2: 3.6VIN, BURST 3: 4.2VIN, BURST 4: 2.5VIN, PULSE SKIP 5: 3.6VIN, PULSE SKIP 6: 4.2VIN, PULSE SKIP
7: POWER LOST, 2.5VIN, BURST 8: POWER LOST, 2.5VIN, PULSE SKIP 9: POWER LOST, 3.6VIN, BURST 10: POWER LOST, 3.6VIN, PULSE SKIP 11: POWER LOST, 4.2VIN, BURST 12: POWER LOST, 4.2VIN, PULSE SKIP
Efficiency vs Load Current VOUT = 2.5V
100 90 80 70 EFFICIENCY (%) 60 50 40 30 20 10 0 0.1 1 10 100 LOAD CURRENT (mA) 1000
3409 G04
BURST 2.7VIN 4.2VIN 3.6VIN 3.6VIN 2.7VIN 4.2VIN PULSE SKIP
70 EFFICIENCY (%) 60 50 40 30 20 10 0 0.1 1 10 100 LOAD CURRENT (mA) 1000
3409 G05
REFERENCE VOLTAGE (V)
4
UW
Efficiency vs Input Voltage VOUT = 1.2V, Burst Mode Operation
1.0
100 90 100 90 80 70 60 50 40 30 20 10 0
Efficiency vs Input Voltage VOUT = 1.2V, Pulse Skip
IOUT = 600mA IOUT = 800mA IOUT = 100mA IOUT = 10mA IOUT = 1mA IOUT = 0.1mA
0.1
POWER LOSS (mW)
80 70
0
4.5 3.5 INPUT VOLTAGE (V)
1.5
2.5
4.5 3.5 INPUT VOLTAGE (V)
5.5
3409 G03
Efficiency vs Load Current VOUT = 1.2V
100 90 80 BURST 2.5VIN 1.6VIN
0.618 0.617 0.616 0.615 0.614 0.613 0.612 0.611 0.610 0.609
Reference Voltage vs Temperature
3.1VIN
3.1VIN 2.5VIN
1.6VIN PULSE SKIP
0.608 -50 -30 -10 10 30 50 70 90 110 130 150 TEMPERATURE (C)
1011 G06
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LTC3409 TYPICAL PERFOR A CE CHARACTERISTICS
(From Typical Application on the front page except for the resistive divider resistor values) Oscillator Frequency vs Temperature
2.70 2.60 2.50 2.40 2.30 2.20 2.10 2.00 1.90 1.80 1.70 1.60 1.50 1.40 1.30 1.20 -50 6
OSCILLATOR FREQUENCY SHIFT (%)
VIN = 2.7V VIN = 1.6V VIN = 4.2V OSC 2.6MHz
OSCILLATOR FREQUENCY (MHz)
OUTPUT VOLTAGE (V)
VIN = 4.2V
OSC 1.7MHz
VIN = 1.6V
VIN = 2.7V
-25
50 25 75 0 TEMPERATURE (C)
RDS(ON) vs Input Voltage
0.450 0.400 0.350 0.300 MAIN SWITCH
MAIN SWITCH 0.50 0.45 0.40 4.2V 2.7V 1.6V 1.6V
DYNAMIC SUPPLY CURRENT, PULSE SKIP (A)
0.250 0.200 0.150 0.100 0.050 0 1.5 2.5 4.5 3.5 INPUT VOLTAGE (V) 5.5
3409 G10
RDS(ON) ()
RDS(0N) ()
SYNCHRONOUS SWITCH
Dynamic Supply Current vs Temperature, VIN = 3.6V, VOUT = 1.5V, 0 Load
500 450
DYNAMIC SUPLLY CURRENT (A)
400 350 300 250 200 150 100 50 0 -50 -25
SWITCH LEAKAGE (nA)
4000 3000 MAIN SWITCH 2000 SYNCHRONOUS SWITCH 1000 0 -50 -25
SWITCH LEAKAGE (nA)
PULSE SKIP
BURST
50 25 0 75 TEMPERATURE (C)
UW
100
3409 G07
Oscillator Frequency Shift vs Input Voltage
1.22
fLOW 1.7MHz 4 2 0 -2 -4 -6 -8 -10 1.5 3.5 2.5 4.5 INPUT VOLTAGE (V)
Output Voltage vs Load Current VIN = 1.6V
1.21 1.2VOUT BURST 1.20 1.2VOUT PULSE SKIP 1.19
fHIGH 2.6MHz
125
1.18
5.5
3409 G08
0 100 200 300 400 500 600 700 800 900 LOAD CURRENT (mA)
3409 G09
RDS(ON) vs Input Temperature
0.55
6000
Dynamic Supply Current vs Input Voltage
DYNAMIC SUPPLY CURRENT, BURST/SLEEP (A)
120 BURST/SLEEP 5000 4000 3000 2000 1000 0 1.5 2 2.5 3 3.5 4 4.5 5 INPUT VOLTAGE (V) 5.5 6 PULSE SKIP VOUT = 1.5V IOUT = 0 VFB = 0 VOUT = 1.5V IOUT = 0 100 80 VFB = VIN 60 40 20 0
0.35 0.30 0.25 0.20 0.15
2.7V 4.2V
SYNCHRONOUS SWITCH 0.10 -50 -25 50 25 75 0 TEMPERATURE (C) 100 125
3409 G11
3409 G12
Switch Leakage vs Temperature VIN = 5.5V
6000 5000 VIN = 5.5V
45 40 35 30 25
Switch Leakage vs Input Voltage
MAIN SWITCH 20 15 10 5 SYNCHRONOUS SWITCH 0 2 4 INPUT VOLTAGE (V) 6 8
3409 G15
100
125
50 25 75 0 TEMPERATURE (C)
100
125
0
3409 G13
3409 G14
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LTC3409 TYPICAL PERFOR A CE CHARACTERISTICS
(From Typical Application on the front page except for the resistive divider resistor values) Start-Up from Shutdown
RUN 2V/DIV
VOUT 1V/DIV INDUCTOR CURRENT 500mA/DIV 200s/DIV
3409 G16
Load Step 50mA to 600mA Pulse Skip
VOUT 20mV/DIV VSWITCH 2V/DIV INDUCTOR CURRENT 200mA/DIV
20s/DIV
3409 G18
VOUT 100mV/DIV
ILOAD 500mA/DIV INDUCTOR CURRENT 500mA/DIV
Load Step 0mA to 600mA Burst Mode Operation
VOUT 100mV/DIV
ILOAD 500mA/DIV INDUCTOR CURRENT 500mA/DIV 20s/DIV
3409 G20
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Load Step 0mA to 600mA Pulse Skip
VOUT 100mV/DIV
ILOAD 500mA/DIV INDUCTOR CURRENT 500mA/DIV 20s/DIV
3409 G17
Burst Mode Operation ILOAD = 35mA
2s/DIV
3409 G19
Load Step 50mA to 600mA Burst Mode Operation
VOUT 100mV/DIV
ILOAD 500mA/DIV INDUCTOR CURRENT 500mA/DIV 20s/DIV
3409 G21
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LTC3409
PI FU CTIO S
VFB (Pin 1): Feedback Pin. Receives the feedback voltage from an external resistive divider across the output. GND (Pin 2): Ground Pin. VIN (Pins 3, 4): Main Supply Pins. Must be closely decoupled to GND, Pin 2 and Pin 9, with a 4.7F or greater ceramic capacitor. MODE (Pin 5): Mode Select Input. To select pulse skipping mode, force this pin above 1.1V. Forcing this pin below 0.3V selects Burst Mode operation. Do not leave MODE floating. SW (Pin 6): Switch Node Connection to Inductor. This pin connects to the drains of the internal main and synchronous power MOSFET switches. RUN (Pin 7): Run Control Input. Forcing this pin above 1.1V enables the part. Forcing this pin below 0.3V shuts down the device. In shutdown, all functions are disabled drawing <1A supply current. Do not leave RUN floating. SYNC (Pin 8): External CLK Input/Fixed Switching Frequency Selection. Forcing this pin above 1.1V for greater than 30s selects 2.6MHz switching frequency. Forcing this pin below 0.3V for greater than 30s selects 1.7MHz switching frequency. External clock input, 1MHz to 3MHz frequency range. When the SYNC pin is clocked in this frequency range the SYNC threshold is nominally 0.63V. To allow for good noise immunity, SYNC signal should swing at least 0.3V below and above this nominal value (0.33V to 0.93V). Do not leave SYNC floating. GND (Pin 9): Exposed Pad. The Exposed Pad is ground. It must be soldered to PCB ground to provide both electrical contact and optimum thermal performance.
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LTC3409
FU CTIO AL DIAGRA
MODE 5
SYNC 8 PLL
SLOPE COMP OSC
VFB 1 0.613V
EA
SOFTSTART VIN RUN 7 REFERENCE 0.675 SHUTDOWN
+
OVDET
-
OPERATIO
Main Control Loop The LTC3409 uses a constant frequency, current mode step-down architecture. Both the main (P-channel MOSFET) and synchronous (N-channel MOSFET) switches are internal. During normal operation, the internal top power MOSFET is turned on each cycle when the oscillator sets the RS latch, and turned off when the current comparator, ICOMP, resets the RS latch. The peak inductor current at which ICOMP resets the RS latch is controlled by the output of error amplifier EA. The VFB pin, described in the Pin Functions section, allows EA to receive an output feedback voltage from an external resistive divider. When the load current increases, it causes a slight decrease in the feedback voltage relative to the 0.613V reference, which in turn, causes the EA amplifier's output voltage to increase until the average inductor current matches the new load current. While the top MOSFET is off, the bottom MOSFET is turned on until either the inductor current
starts to reverse, as indicated by the current reversal comparator IRCMP, or the beginning of the next clock cycle. Comparator OVDET guards against transient overshoots >10% by turning the main switch off and keeping it off until the transient has ended. Burst Mode Operation The LTC3409 is capable of Burst Mode operation in which the internal power MOSFETs operate intermittently based on load demand. To enable Burst Mode operation, simply connect the MODE pin to GND. To disable Burst Mode operation and enable PWM pulse skipping mode, connect the MODE pin to VIN or drive it with a logic high (VMODE >1.1V). In this mode, the efficiency is lower at light loads, but becomes comparable to Burst Mode operation when the output load exceeds 30mA. The advantage of pulse
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-
IRCMP
+
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0.65V VIN
- +
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- +
0.4V
3, 4
- +
EN SLEEP
-
BURST Q Q SWITCHING LOGIC AND BLANKING CIRCUIT
ICOMP
+
5
S R
RS LATCH
ANTISHOOTTHRU
6 SW
OV
2 GND
3409 FD
LTC3409
OPERATIO
skipping mode is lower output ripple and less interference to audio circuitry. When the converter is in Burst Mode operation, the minimum peak current of the inductor is set to approximately 200mA regardless of the output load. Each burst event can last from a few cycles at light loads to almost continuously cycling with short sleep intervals at moderate loads. In between these burst events, the power MOSFETs and any unneeded circuitry are turned off, reducing the quiescent current to 65A. In this sleep state, the load current is being supplied solely from the output capacitor. As the output voltage droops, the EA amplifier's output rises above the sleep threshold signaling the BURST comparator to trip and turn the top MOSFET on. This process repeats at a rate that is dependent on the load demand. Short-Circuit Protection When the output is shorted to ground the LTC3409 limits the synchronous switch current to 1.5A. If this limit is exceeded, the top power MOSFET is inhibited from turning on until the current in the synchronous switch falls below 1.5A. Dropout Operation As the input supply voltage decreases to a value approaching the output voltage, the duty cycle increases toward the maximum on-time. Further reduction of the supply voltage forces the main switch to remain on for more than one cycle.
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Slope Compensation Slope compensation provides stability in constant frequency architectures by preventing subharmonic oscillations at high duty cycles. It is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. User Controlled Switching Frequency The internal oscillator of the LTC3409 can be synchronized to a user-supplied external clock applied to the SYNC pin. Alternately, when this pin is held at a fixed High or Low level for more than 30s, the internal oscillator will revert to fixed-frequency operation; where the frequency may be selected as 1.7MHz (SYNC Low) or 2.6MHz (SYNC High). Internal Soft-Start At start-up when the RUN pin is brought high, the internal reference is linearly ramped from 0V to 0.613V in 1ms. The regulated feedback voltage will follow this ramp resulting in the output voltage ramping from 0% to 100% in 1ms. The current in the inductor during soft-start will be defined by the combination of the current needed to charge the output capacitance and the current provided to the load as the output voltage ramps up. The start-up waveform, shown in the Typical Performance Characteristics, shows the output voltage start-up from 0V to 1.5V with a 2.5 load and VIN = 2.2V. The 2.5 load results in an output of 600mA at 1.5V.
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LTC3409
APPLICATIO S I FOR ATIO
The basic LTC3409 application circuit is shown on the first page of this data sheet. External component selection is driven by the load requirement and begins with the selection of L followed by CIN and COUT. Inductor Selection For most applications, the value of the inductor will fall in the range of 1H to 10H. Its value is chosen based on the desired ripple current. Large value inductors lower ripple current and small value inductors result in higher ripple currents. Higher VIN or VOUT also increases the ripple current as shown in Equation 1. A reasonable starting point for setting ripple current is IL = 240mA (40% of 600mA).
IL = V 1 VOUT 1 - OUT f *L VIN
The DC current rating of the inductor should be at least equal to the maximum load current plus half the ripple current to prevent core saturation. Thus, a 720mA rated inductor should be enough for most applications (600mA + 120mA). For better efficiency, choose a low DC resistance inductor. The inductor value also has an effect on Burst Mode operation. The transition to low current operation begins when the inductor current peaks fall to approximately 200mA. Lower inductor values (higher IL) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to increase. Inductor Core Selection Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don't radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. The choice of which style inductor to use often depends more on the price vs size requirements and any radiated field/EMI requirements than on what the LTC3409 requires to operate. Table 1 shows some typical surface mount inductors that work well in LTC3409 applications.
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Table 1. Representative Surface Mount Inductors
PART NUMBER Sumida CDRH3D18/LD Sumida CDRH2D11 Sumida CMD4D11 Murata LQH32CN Toko D312F Panasonic ELT5KT VALUE (H) 2.2 3.3 1.5 2.2 2.2 3.3 1.0 2.2 2.2 3.3 3.3 4.7 DCR ( MAX) 0.041 0.054 0.068 0.170 0.116 0.174 0.060 0.097 0.060 0.260 0.17 0.20 MAX DC SIZE CURRENT (A) W x L x H (mm3) 0.85 0.75 0.90 0.78 0.950 0.770 1.00 0.79 1.08 0.92 1.00 0.95 3.2 x 3.2 x 2.0 3.2 x 3.2 x 1.2 4.4 x 5.8 x 1.2 2.5 x 3.2 x 2.0 2.5 x 3.2 x 2.0 4.5 x 5.4 x 1.2
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(1)
CIN and COUT Selection In continuous mode, the source current of the top MOSFET is a square wave of duty cycle VOUT/VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by:
[VOUT (VIN - VOUT )]1/2 CIN Re quired IRMS IOUT(MAX)
VIN This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that the capacitor manufacturer's ripple current ratings are often based on 2000 hours of life. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Always consult the manufacturer if there is any question. The selection of COUT is driven by the required effective series resistance (ESR). Typically, once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. The output ripple DVOUT is determined by:
1 VOUT = IL ESR + 8 * f * COUT
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LTC3409
APPLICATIO S I FOR ATIO
where f = operating frequency, COUT = output capacitance and IL = ripple current in the inductor. For a fixed output voltage, the output ripple is highest at maximum input voltage since IL increases with input voltage. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalum. These are specially constructed and tested for low ESR so they give the lowest ESR for a given volume. Other capacitor types include Sanyo POSCAP, Kemet T510 and T495 series, and Sprague 593D and 595D series. Consult the manufacturer for other specific recommendations. Using Ceramic Input and Output Capacitors Higher value, lower cost ceramic capacitors are now available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. Because the LTC3409's control loop does not depend on the output capacitor's ESR for stable operation, ceramic capacitors can be used to achieve very low output ripple and small circuit size. However, care must be taken when these capacitors are used at the input and the output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN, large enough to damage the part. When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size.
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Output Voltage Programming The output voltage is set by a resistive divider according to the following formula: R1 VOUT = 0.613V 1 + R2 The external resistive divider is connected to the output, allowing remote voltage sensing as shown in Figure 1.
VOUT R1 VFB LTC3409 GND
3409 F01
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R2
Figure 1
Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% - (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses in LTC3409 circuits: VIN quiescent current and I2R losses. The VIN quiescent current loss dominates the efficiency loss at very low load currents whereas the I2R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence as illustrated in Figure 2.
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LTC3409
APPLICATIO S I FOR ATIO
1 BURST PULSE SKIP 0.1 POWER LOSS (W)
0.01
2.5VIN 3.6VIN 4.2VIN
0.001
4.2VIN 3.6VIN 2.5VIN 1 10 100 LOAD CURRENT (mA) 1000
3409 F02
0.0001 0.1
Figure 2
1. The VIN quiescent current is due to two components: the DC bias current as given in the Electrical Characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge, dQ, moves from VIN to ground. The resulting dQ/dt is the current out of VIN that is typically larger than the DC bias current. In continuous mode, IGATECHG = (QT + QB) where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias and gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages. 2. I2R losses are calculated from the resistances of the internal switches, RSW, and external inductor RL. In continuous mode, the average output current flowing through inductor L is "chopped" between the main switch and the synchronous switch. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 - DC) The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics. Thus, to obtain I2R losses, simply add RSW to RL and multiply the result by the square of the average output current.
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Other losses including CIN and COUT ESR dissipative losses and inductor core losses generally account for less than 2% total additional loss. Thermal Considerations In most applications the LTC3409 does not dissipate much heat due to its high efficiency. But, in applications where the LTC3409 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 150C, both power switches will be turned off and the SW node will become high impedance. To avoid the LTC3409 from exceeding the maximum junction temperature, the user will need to do a thermal analysis. The goal of the thermal analysis is to determine whether the operating conditions exceed the maximum junction temperature of the part. The temperature rise is given by: TR = (PD)(JA) where PD is the power dissipated by the regulator and JA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: TJ = TA + TR where TA is the ambient temperature. As an example, consider the LTC3409 in dropout at an input voltage of 1.6V, a load current of 600mA and an ambient temperature of 75C. From the typical performance graph of switch resistance, the RDS(ON) of the P-channel switch at 75C is approximately 0.48. Therefore, power dissipated by the part is: PD = ILOAD2 * RDS(ON) = 172.8mW For the DD8 package, the JA is 43C/W. Thus, the junction temperature of the regulator is: TJ = 75C + (0.1728)(43) = 82.4C which is well below the maximum junction temperature of 125C.
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LTC3409
APPLICATIO S I FOR ATIO
Note that at higher supply voltages, the junction temperature is lower due to reduced switch resistance (RDS(ON)). Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to (ILOAD * ESR), where ESR is the effective series resistance of COUT. ILOAD also begins to charge or discharge COUT, which generates a feedback error signal. The regulator loop then acts to return VOUT to its steady state value. During this recovery time VOUT can be monitored for overshoot or ringing that would indicate a stability problem. For a detailed explanation of switching control loop theory, see Application Note 76. A second, more severe transient is caused by switching in loads with large (>1F) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25 * CLOAD). Thus, a 10F capacitor charging to 3.3V would require a 250s rise time, limiting the charging current to about 130mA. Board Layout Considerations When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3409. These items are also illustrated graphically in the layout diagram of Figure 3. Check the following in your layout. 1. Does the capacitor CIN connect to the power VIN (Pins 3, 4) and GND (Exposed Pad) as close as possible? This capacitor provides the AC current to the internal power MOSFETs and their drivers.
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2. Are the COUT and L1 closely connected? The (-) plate of COUT returns current to GND and the (-) plate of CIN. 3. The resistor divider, R1 and R2, must be connected between the (+) plate of COUT and a ground sense line terminated near GND (Exposed Pad). The feedback signals VFB should be routed away from noisy components and traces, such as the SW line (Pins 6), and its trace should be minimized. 4. Keep sensitive components away from the SW pins. The input capacitor CIN and the resistors R1 and R2 should be routed away from the SW traces and the inductors. 5. A ground plane is preferred, but if not available, keep the signal and power grounds segregated with small signal components returning to the GND pin at one point. They should not share the high current path of CIN or COUT. 6. Flood all unused areas on all layers with copper. Flooding with copper will reduce the temperature rise of power components. These copper areas should be connected to VIN or GND.
VIN CIN VIN RUN VFB VIN SYNC MODE SW SGND GND C1 L1 VOUT LTC3409 COUT R2 R1
3409 F03
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Figure 3
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LTC3409
APPLICATIO S I FOR ATIO
Design Example
As a design example, assume the LTC3409 is used in a 2-alkaline cell battery-powered application. The VIN will be operating from a maximum of 3.2V down to about 1.8V. The load current requirement is a maximum of 600mA but most of the time it will be in standby mode, requiring only 2mA. Efficiency at both low and high load currents is important. Output voltage is 1.5V. With this information we can calculate L using Equation 2:
L= V 1 VOUT 1 - OUT f * IL VIN
Substituting VOUT = 1.5V, VIN = 3.2V, IL = 240mA and f = 1.7MHz in Equation 2 gives: L= 1 1.5 1.5 1 - 2.2H 1.7MHz * 240mA 3.2
VIN 1.6V TO 5.5V CIN 4.7F
R2 133k
LTC3409 L1 2.2H COUT 10F CER
3409 F04
GND VIN VIN R1 191k
RUN SW MODE
EFFICIENCY (%)
VFB
SYNC VOUT 1.5V 0.6A
L1: SUMIDA CDRH2D18/LD C1 10pF
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For best efficiency choose a 750mA or greater inductor with less than 0.3 series resistance. CIN will require an RMS current rating of at least 0.3A ILOAD(MAX)/2 at temperature. For the feedback resistors, choose R2 = 133k. R1 can then be calculated from Equation 2 at 191K. Figure 4 shows the complete circuit along with its efficiency curve. Table 2 below gives 1% resistor values for selected output voltages.
VOUT 0.85V 1.2V 1.5V 1.8V R1 51.1k 127k 191k 255k R2 133k 133k 133k 133k
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(2)
Burst Mode Efficiency, 1.5VOUT
100 90 80 70 60 50 40 30 20 10 0 0.1 1 10 100 LOAD CURRENT (mA) 1000
3409 F04b
1.8VIN 3.2VIN 2.5VIN
Figure 4
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LTC3409
PACKAGE DESCRIPTIO
3.5 0.05 1.65 0.05 2.15 0.05 (2 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 BSC 2.38 0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP 5 0.38 0.10 8
PIN 1 TOP MARK (NOTE 6)
(DD8) DFN 1203
0.200 REF
NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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DD Package 8-Lead Plastic DFN (3mm x 3mm)
(Reference LTC DWG # 05-08-1698)
0.675 0.05 3.00 0.10 (4 SIDES) 1.65 0.10 (2 SIDES) 0.75 0.05 4 0.25 0.05 2.38 0.10 (2 SIDES) BOTTOM VIEW--EXPOSED PAD 1 0.50 BSC 0.00 - 0.05
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LTC3409
TYPICAL APPLICATIO
2-Cell to 1.2V/600mA Regulator for High Efficiency and Low Profile
VIN 1.8V TO 3V 3, 4 CIN 4.7F CER 7 5 8 LTC3409 6 SW VIN RUN MODE SYNC GND 9 SGND 2 CIN: TDK C1608X5R0J475M COUT: TDK C1608X5R0G106M *SUMIDA CDRH2D09NP-2R2NC VFB 1 301k 287k 2.2H* 22pF VOUT COUT 1.2V 10F CER
Efficiency
95 VIN = 1.8V 90 VOUT = 1.2V 85 f = 1.7MHz f = 2.6MHz
EFFICIENCY (%)
80 75 70 65 60 55 50 0.0001 0.01 0.001 0.1 OUTPUT CURRENT (mA) 1
3409 TA02b
RELATED PARTS
PART NUMBER LTC1878 LTC1879 LT3020 LTC3025 LTC3404 LTC3405/LTC3405A LTC3406/LTC3406B LTC3407 LTC3411 DESCRIPTION 600mA (IOUT), 550kHz, Synchronous Step-Down DC/DC Converter 1.20A (IOUT), 550kHz, Synchronous Step-Down DC/DC Converter 100mA, Low Voltage VLDOTM 100mA, Low Voltage VLDO 600mA (IOUT), 1.4MHz, Synchronous Step-Down DC/DC Converter 300mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converter 600mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converter Dual, 600mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converter 1.25A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter COMMENTS 96% Efficiency, VIN: 2.7V to 6V, VOUT(MIN) = 0.8V, IQ = 10A, ISD < 1A, MS8 Package 95% Efficiency, VIN: 2.7V to 10V, VOUT(MIN) = 0.8V, IQ = 15A, ISD < 1A, 16-Lead TSSOP VIN: 0.9V to 10V, VOUT(MIN) = 0.20V, Dropout Voltage = 0.15V, IQ = 120A, ISD < 3A, VOUT = ADJ, DFN/MS8 Packages VIN: 0.9V to 5.5V, VOUT(MIN) = 0.40V, Dropout Voltage = 0.05V, IQ = 54A, ISD < 1A, VOUT = ADJ, DFN Package 96% Efficiency, VIN: 2.7V to 6V, VOUT(MIN) = 0.8V, IQ = 10A, ISD < 1A, MS8 Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 20A, ISD < 1A, ThinSOTTM Package 96% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 20A, ISD < 1A, ThinSOT Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40A, ISD < 1A, 10-Lead MSE Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60A, ISD < 1A, 10-Lead MS Package
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VLDO and ThinSOT are trademarks of Linear Technology Corporation.
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
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3409 TA02a
Load Step
VOUT 100mV/DIV AC COUPLED IL 500mA/DIV ILOAD 500mA/DIV 20s/DIV VIN = 1.8V VOUT = 1.2V ILOAD = 200mA TO 600mA
3409 TA02c
LT/TP 0205 1K * PRINTED IN THE USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2005

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